1. Field of the Invention
The present invention relates generally to a carrier board, and more particularly to a semiconductor package substrate.
2. Description of Related Art
In order to meet ever-increasing demands for advanced electronic products with multi-functions, a ball grid array (BGA) type packaging technique is frequently employed and becomes very popular as such packaging technique is capable of providing a sufficient amount of input/out (I/O) connections for connecting high-density electronic components and electronic circuits.
Along with continuous improvements in semiconductor packaging technology, the amount and the density of I/O connections are drastically increased in a BGA package. In view of this, an increasing amount of finger pads corresponding to the amount of I/O connections must be formed on a substrate to act as external electrical connecting terminals of a semiconductor chip, so as to allow the semiconductor chip to be electrically connected external circuits through the finger pads by means of wire bonding.
A known layout of finger pads on a substrate, which is similar to what has been disclosed by U.S. Pat. Nos. 6,465,891 and 6,531,762, has a plurality of finger pads disposed around the periphery of a semiconductor chip at equal intervals, wherein a plurality of bonding wires are employed to respectively electrically connect bonding pads of the semiconductor chip to the finger pads of the substrate, so as to form external electrical connections of the chip.
The amount of I/O connections may be increased to improve electrical functionality of the semiconductor package, wherein the amount of the bonding pad of the chip and the finger pads of the substrate may be increased accordingly. However, in order to achieve such arrangement, pitches between the finger pads have to be reduced to a certain level. Moreover, the finger pads shall be disposed in position near the chip to shorten the length of the bonding wires, in order to improve electrical functionality and reduce production cost.
Referring to FIG. 1, a prior-art layout of finger pads on a substrate, which can shorten the length of bonding wires, is disclosed by U.S. Pat. No. 5,898,213. In the prior art, a plurality of finger pads 111 and its adjacent finger pads 112 are staggered around the periphery of a chip 12, wherein, hereinafter, the foregoing finger pads that are closer to the center of the chip 12 are referred as the first finger pads 111 and the ones that are further from the center of the chip 12 are referred as the second finger pads 112. Moreover, a plurality of bonding wires 13 are employed for electrically connecting bonding pads 122 on the chip 12 to the finger pads 111, 112 on the substrate. As the first finger pads 111 and the second finger pads 112 are disposed in a staggered pattern, the pitch distance Q between the finger pads 111, 112 is thus reduced, thereby reducing the length and the wire bonding distance of the bonding wires.
The foregoing technique may reduce the patch distance between the first finger pads 111 and the second finger pads 112. In practical implementation, a bonder is employed for connecting the chip 12 to the first finger pads 111 and then to the second finger pads 112 via bonding wires 13. However, because the size, shape and location of the second finger pads 112 are very close to that of lead traces of the first finger pads 111, the bonder can hardly distinguish the second finger pads 112 from the lead traces of the first finger pads 111, thereby frequently, mistakenly recognizing lead traces formed at the rear portions of the first finger pads 111 as the second finger pads 112 and erroneously bonding the bonding wires to the lead traces of the first finger pads 111 rather than the second finger pads 112 (such incorrect bonding is shown in FIG. 1 by a dotted line). Moreover, such wire bonding error may lead to short circuit and even jeopardize the entire semiconductor package.
Furthermore, referring to FIG. 2, another known layout of finger pads on a substrate is disclosed in U.S. Pat. No. 5,444,303, which is capable of reducing the length of bonding wires. In such prior-art layout, a plurality of finger pads 21 are disposed in rows, wherein the finger pads 21 are trapezium-shaped or reverse trapezium-shaped, with one longer side thereof parallel to an one shorter side thereof. Moreover, the longer side of one of the finger pads 21 may be closer to the chip 22, whereas the longer side of the one of the adjacent finger pads 21 may have the longer side further from the chip 22. In addition, a plurality of bonding wires 23 are employed for electrically connecting bonding pads 222 on the chip 22 to the finger pads 21 on the substrate.
Similarly, due to the trapezium-shaped finger pads, although the wire bonding distance is reduced in aforesaid technique, when bonding wire is bonded to short side of a finger pad close to the chip, the bonding wire is easy to sag down and contact adjacent finger pad, thus resulting in electrical short circuit, as indicated by a label S in FIG. 2. Particularly for bonding wires disposed at farther outer side of the substrate, the longer and the higher the bonding wires, the easier the bonding wires sag down and contact adjacent finger pads. Hence, the reliability of the process is adversely affected.
Therefore, there is a need to prevent wire bonding error and electrical short circuit problem caused by faulty contact of bonding wire with adjacent finger pad while reducing the wire bonding distance.